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| rev. 1.20 1 november 17, 2016 rev. 1.00 pb november 17, 2016 HT7L5820/ht7l5821 integrated pfc and quasi-resonant current mode pwm controller application circuits HT7L5820 ht7l5821 ac 16 13 14 hvs zcd opfc 6 cspfc 4 inv 3 sel 1 vin vss 9 opwm 8 cspwm 5 vcc 7 det 10 fb 11 rt comp 12 2 nc 15 features ? integrated t ransition mode (tm) pfc controller and quasi-resonant (qr) fyback controller ? wide ac input range from 85v ac to 265v ac ? integrated 650v jfet quick high voltage start-up ? integrated thd pfc stage optimiser ? brown-out and brown-in protection ? internal accurate feedback reference voltage: 2% ? internal 9.6ms pwm soft-start ? high/low line over-power compensation ? fb pin protection (auto recovery) ? over-power and overload protection ? short-circuit protection ? open-loop protection ? external triggering and adjustabe over -temperature protection C rt pin ? vcc pin ovp C latched ? internal over-temperature shutdown C 140c ? 16-pin n sop package applications ? ac/dc nb ad apters ? open-frame smps ? battery chargers ? general led lighting applications ? industria l, commercial, and residential fxtures general description the ht 7l5820/ht7l5821 i s highl y i ntegrated de vice which i ncludes a powe r fa ctor c orrection c ontroller and quasi-resonant flyback controller . the high level of functional integration provides the means for very cost-effective de signs wi th a m inimum of e xternal components. in the pfc stage the device uses a transition mode to provide a re gulated ou tput vo ltage wi th l ow syst em costs, low harmonic distortion and high power factor . for qr fyback the device provides higher effciencies and low er em i when compared with conventional pwm systems. the devic e also includes a range of features to protect the controller from fault conditions. these include secondary side open-loop and over -current protection, vcc pin over -voltage protection, det pin over - voltage for out put over -voltage protecti on, brown- in/out ac input voltage, internal over -temperature shutdown a nd a djustable ove r-temperature prot ection using the rt pin with an external ntc resistor. selection table part no. HT7L5820 ht7l5821 protection mode internal otp auto- recovery latched rt pin otp rt pin triggering output voltage ovp
rev. 1.20 2 november 17, 2016 HT7L5820/ht7l5821 block diagram 11 qr control logic vss 9 12 ovp 10 det 5 cspwm fb internal soft start valley detector current limit rt 0.5v otp brown in/out pfc select 13 vin 8 opwm vcc 16 hvs 7 vdd ovp uvlo voltage regulator pfc control logic zero current detector 14 zcd 6 opfc 15 nc 0.8v cspfc 4 + comp 2 e/a 2.5v 3 inv pfc select sel 1 inv ovp inv uvp inv ovp inv uvp inv ovp inv uvp pin assignment hvs nc zcd vin rt fb det vss HT7L5820/ht7l5821 16 nsop-a sel comp inv cspfc cspwm opfc vcc opwm 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 rev. 1.20 3 november 17, 2016 HT7L5820/ht7l5821 pin description pin no. symbol description 1 sel pfc output selected pin 2 comp pfc compensation pin, a capacitor should be placed between comp and vss 3 inv voltage sense for pfc output, regulation voltage is 2.5v 4 cspfc current sense pin. a resistor is connected to sense the pfc mosfet current 5 cspwm current sense pin. a resistor is connected to sense the flyback mosfet current 6 opfc gate drive output to drive the external mosfet for pfc 7 vcc power supply pin 8 opwm gate drive output to drive the external mosfet for flyback 9 vss ground pin 10 det zero-current detect pin for flyback 11 fb voltage feedback pin for flyback. connect a photo-coupler for system regulation 12 rt external protection triggering 13 vin sense input for mains voltage 14 zcd zero-current detect pin for pfc 15 nc no connection 16 hvs hvs pin is connected to the ac line voltage through a resistor absolute maximum ratings parameter value unit vcc supply voltage -0.3 to 30 v hvs voltage -0.3 to 650 v sel, comp, inv, cspfc, cspwm, fb, rt, vin -0.3 to 6 v maximum current at zcd, det 3 (source), 3 (sink) ma operating junction temperature -40 to 150 c storage temperature range -55 to 150 c maximum junction temperature 150 c recommended operating parameter value unit operating ambient temperature -40 to 105 c rev. 1.20 4 november 17, 2016 HT7L5820/ht7l5821 electrical characteristics v cc =15v, ta=-40~105c (ta=t j ), unless otherwise specifed symbol parameter conditions min. typ. max. unit v cc section v op continuous operation voltage 25 v v cc-on turn-on threshold voltage 15 16.5 18 v v cc-pwm-off pwm off threshold voltage 9 10 11 v v cc-off turn-off threshold voltage 7 8 9 v i dd-st startup current v cc =v cc-on -0.16v, gate open 20 a i dd-op operating current v cc =15v, opfc, opwm=100khz, c l-pfc , c l-pwm =2nf 10 ma i dd-green green mode operating supply current (average) v cc =15v, c l-pwm =2nf opwm=450hz 5.5 ma i dd-pwm-off operating current at pwm-off phase v cc =v cc-pwm-off - 0.5v 70 120 170 a v cc-ovp v cc over-voltage protection (latch-off) 26 28 30 v t vcc-ovp v cc ovp debounce time 100 150 200 s i dd-latch v cc over-voltage protection latch-up holding current v cc =7.5v 120 a hvs startup current source section v hvs-min minimum startup voltage on hvs pin 50 v i hvs supply current drawn from hvs pin v ac =90v (v dc =120v), v cc =0v 1.3 ma hvs=500v, v cc =v cc-off +1v 8 a vin and sel section v vin-uvp threshold voltage for ac input under-voltage protection 0.85 0.9 0.95 v v vin-re-uvp under-voltage protection reset voltage (for startup) 1.2 1.25 1.3 v t vin-uvp under-voltage protection debounce time (no need at startup and hiccup mode) 70 120 170 ms v vin-sel-h high v vin threshold for sel comparator sel ground 2.45 2.5 2.55 v v vin-sel-l low v vin threshold for sel comparator sel open 2.25 2.3 2.35 v t sel sel-enable debounce time 70 120 170 ms v sel-ol output low voltage of sel pin io=0.1ma 1 v t on-max-pfc pfc maximum on time cspfc=0v,comp=5.5v 32 40 48 s pwm stage a v input-voltage to current sense attenuation (note) a v =v cs /v fb , 0 rev. 1.20 5 november 17, 2016 HT7L5820/ht7l5821 symbol parameter conditions min. typ. max. unit det pin ovp and valley detection section v det-ovp comparator reference voltage 2.45 2.5 2.55 v t det-ovp output ovp debounce time 100 170 240 s v det-high upper clamp voltage i det =1ma 5.7 v v det-low lower clamp voltage i det =-1ma -0.4 v t valley-delay delay time from valley signal detected to output turn-on (note) 150 200 250 ns t off-bnk leading-edge blanking time for det-ovp (2.5v) and valley signal when pwm mos turns off (note) 3 4 5 s t time-out time-out after t off-min 5 6 7 s pwm oscillator section t on-max-pwm maximum on time 38 46 54 s t off-min minimum off time v fb v n 7 8.5 10 s v fb =v g 31 36 41 s v n beginning of green-on mode at fb voltage level 1.95 2.1 2.25 v v g beginning of green-off mode at fb voltage level 1.05 1.2 1.35 v v g hysteresis for beginning of green-off mode at fb voltage level 0.1 v v ctl-pfc-off threshold voltage on fb pin to disable pfc sel open 1.5 1.55 1.6 v sel ground 1.5 1.55 1.6 v v ctl-pfc-on threshold voltage on fb pin to enable pfc sel open 1.85 1.9 1.95 v sel ground 1.7 1.75 1.8 v t pfc-off pfc disable debounce time to disable pfc pfc status from on to off 400 600 800 ms t pfc-on pfc disable debounce time to enable pfc pfc status from off to on 150 s t starter-pwm start timer (time-out timer) v fb rev. 1.20 8 november 17, 2016 HT7L5820/ht7l5821 14.5 15 15.5 16 16.5 17 17.5 18 -40 -25 -10 5 20 35 50 65 80 95 110 125 temp() v clamp (v) 1.8 1.9 2 2.1 2.2 -40 -25 -10 5 20 35 50 65 80 95 110 125 temp() v n (v) pwm gate output clamping voltage beginning of green-on mode at vfb 1 1.1 1.2 1.3 1.4 -40 -25 -10 5 20 35 50 65 80 95 110 125 temp() v g (v) 7.5 8 8.5 9 9.5 -40 -25 -10 5 20 35 50 65 80 95 110 125 temp() t off-min (us) beginning of green-off mode at vfb pwm minimum off-time for vfb > vn 30 32 34 36 38 -40 -25 -10 5 20 35 50 65 80 95 110 125 temp() t off-min (us) -0.6 -0.5 -0.4 -0.3 -0.2 -40 -25 -10 5 20 35 50 65 80 95 110 125 temp() v det-low (v) 2.35 2.4 2.45 2.5 2.55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temp() v det-ovp (v) 100 105 110 115 120 -40 -25 -10 5 20 35 50 65 80 95 110 125 temp() i rt (ua) rev. 1.20 9 november 17, 2016 HT7L5820/ht7l5821 temp(c) v rt-trigger (v) over temperature protection threshold voltage of rt pin functional description pfc stage error amplifer the pfc error amplifier is used for regulating the pfc out put vol tage. t he e rror a mplifier i nput i s t he inv pin and it is connected to a resistor divider from the pfc out put. t he e rror a mplifier i nput vol tage i s compared w ith an internal reference voltage of 2.5v to make the error amplifier s ource or s ink current to char ge and di scharge its output capacitor . the capacitor voltage will determine the on-time of the pfc controller to regulate the output voltage. the sink and source capability of the error amplifier is approximately 30ua during normal the operation and the typical transconductance value is 150s. dynamic response the pfc dy namic re sponse i s ve ry sl ow be cause of the pfc voltage loop low frequency bandw idth. the device provides an enhanced dynamic response for the pfc l oop b y d etecting t he f eedback v oltage o n the inv pin. whenever the inv voltage is lower than the re ference va lue 2.3v , i t wi ll i ncrease t he e rror amplifier t ransconductance and i n t urn i ncrease t he pfc duty cycle directly . this change in duty cycle bypasses the slow change of the comp voltage and thus res ults in a fas t dynamic res ponse for the p fc stage. zcd pin the de vice pe rforms z ero c urrent de tection by usi ng an a uxiliary wi nding on t he pfc boost i nductor. during normal operation, w hen the p fc m os is switched of f, the stored ener gy in the pfc boost inductor will release its ener gy to the output. the voltage on the zcd pin decreases as the stored energy in t he pfc boost i nductor i s re leased t o t he out put. when the zcd pin voltage is low er than 0.7v , the internal zcd comparator is triggered and a pfc gate signal is generated. if no triggering signal is detected o n t he z cd p in, t he d evice wi ll g enerate a restart signal 190s after the last pfc gate signal. the maximum a nd m inimum v oltage o f t he z cd p in i s internally clamped to 5.7v and 0v respectively sel pin a built-in low voltage switch can be turned on or of f according to vin voltage level. the drain pin of this internal switch is connected to the sel pin. brown-in/out protection C vin pin the device features brown-in/out protection using ac voltage detection . the vin pin is used to detect the ac input voltage using a resistor divider . as the ac voltage drops and the v vin voltage drops below 0.9 v for 100ms, the uvp protection function is activated and the comp pin voltage is clamped to around 1.6v . since a lower comp voltage results in a reduced pfc on-time, the ener gy concentration is limited and therefore the pfc output voltage decrease s . w hen the inv pin is lower than 1.2v , the device turns of f all pfc and pwm switching operations and the v cc volt- age enters the hiccup mode . not until the v vin voltage increases beyond 1. 25 v (typical) and v cc reaches its turn-on vol tage a gain wi ll t he pw m a nd pfc ga te signals be generated. peak current limiting C cspfc pin the cspfc pi n i s use d t o se nse t he pfc swi tch current. during normal pfc operation, the voltage on t he c spfc p in i s c ompared wi th a t hreshold voltage of 0.8v using the internal comparator . when the cspfc pin voltage is greater than the threshold voltage, the p fc s witch w ill be turned of f immediately. t he c urrent-sense r esistor i s a djustable to determine the pfc switch peak current. rev. 1.20 10 november 17, 2016 HT7L5820/ht7l5821 output voltage ovp and uvp C inv pin over-voltage a nd un der-voltage pr otection fun ctions are integrated into the device for the pfc stage. both are detected and determined using the inv pin voltage. the ovp or uvp circuit is activated to stop pfc switching operations immediately when the inv pin vo ltage i s gr eater t han 2. 65v or l ess t han 0. 35v. in additio n, the de-bounce time of the ovp and uvp is set to about 70s to avoid overs hoot or abnormal conditions. qr flyback stage startup current C hvs pin for startup purposes the hvs pin is connected to the ac l ine i nput t hrough a re sistor. usi ng a n i ntegrated high-voltage st artup c ircuit, t he d evice p rovides a high current to char ge the external vcc capacitor to reduce the controller s startup time. t o reduce power consumption, when the vcc voltage exceeds the turn-on voltage and enters normal operation, this high voltage startup circuit will be switched of f to avoid power losses due to power consumption in the startup resistor. under-voltage lockout (uvlo) C vcc pin the turn-on, pwm-of f and turn-of f thresholds are fxed internally at 16 v /10v /8v, respectively . during startup, the hold-up capacitor (v cc cap.) is char ged by the hv startup current until the v cc voltage reaches the turn-on voltage. the hold-up capacitor continues to supply v cc until ener gy can be delivered from the auxiliary winding. d uring this startup process , v cc must not drop below v cc pwm-off . this uvlo hyster- this uvlo hyster- this uvlo hyster - esis window ensures that hold-up capacitor is suitable for supply ing v cc during startup. the following fgure shows the v cc waveform in the hiccup mode. v cc-on (16v) v cc-pwm-off (10v) v cc-off (8v) pwm pulse v cc during hiccup mode operation valley detection C det pin the det pin is connected to an auxiliary winding of the trans former using divider res istors. d uring the pw m o ff t ime, wh en t he t ransformer i nductor current dischar ges to zero, the transformer inductor and parasitic capacitors of the pwm switch start to resonate concurrently . as the drain voltage on the pwm switch falls, the voltage on the auxiliary winding v aux decre ases as we ll. then, the int ernal det comparator detects the valley voltage of the switching waveform to achieve valley voltage switching. this ens ures q r operation, minimis es switching losses and reduces emi. the maximum and minimum voltage of the det pi n is int ernally clamped to 5.7v and -0.4v respectively. green-mode and pfc on/off control C fb pin a g reen m ode mechanis m is adopted to reduce switching losses in the power system under condi- under condi- under condi - tions of l ight l oad. t he de vice use s a l inear of f-time modulation to decrease switching frequency accord- switching frequency accord- switching frequency accord - ing to the fb pin voltage. the following fgure shows the fb versus t off-min characteristic curve. as fb pin v oltage is lower than v n (2.1v), the t off-min time increases with lower fb pin voltage. the valley volt- pin voltag e . the valley volt- . the valley volt - age detection signal does not activate until the t off-min time fnishes which extends valley voltage switching during dcm operation and reduces switching losses to o btain h igher c onversion e ffciencies. i n a ddition, in order to reduce the standby power under conditions of no load or very light-load, the fb pin voltage is also used to control the pfc on/of f operation. as the fb voltage falls below the v ctl-pfc-off threshold volt - age the controller will stop pfc switching until the fb pin voltage returns to v ctl-pfc-on . 36us 8us fb(v) v n (2.1v) v g (1.2v) 2.5ms t off-min (s) // pfc-on pfc-off v ctl-pfc-on v ctl-pfc-off fb vs t off-min characteristic curve high/low line over-power compensation C det pin the pow er delivered by a flyback pow er s upply is proportional to the square of the peak current during qr control . however , due to the inherent propagation delay of the logic, the actual peak current is higher for a high input voltage than for a low input voltage. this results in a significant difference between the maxi- difference between the maxi- difference between the maxi - mum output pow er delivered by the power s upply. t o compensate for this variation for a universal input range, the det pin produces an offset voltage to com- the det pin produces an offset voltage to com- the det pin produces an offset voltage to com - pensate the t hreshold v oltage o f t he p eak c urrent l imit. rev. 1.20 11 november 17, 2016 HT7L5820/ht7l5821 this of fset voltage is generated by sensing the current drawn from the det pin when the power switch turns on. the following fgure shows the i det versus v limit characteristic curve. 900 800 700 600 500 400 300 400 300 200 1000 500 600 i det (ua) v limit (mv) i det vs v limit characteristic curve leading edge blanking C leb each time the pfc or pwm switches are turned on, a voltage spike occurs on the current sense resistor . t o avoid faul ty t riggering, a l eading-edge bla nking t ime is built into the device. during the blanking period the current l imit c omparator i s d isabled a nd c annot swi tch off the gate driver. vcc pin over-voltage protection C vcc ovp t he vc c ovp f unction i s u sed t o p revent d evice damage. if the v cc voltage is higher than v cc-ovp and l asts for a t ime t vcc-ovp , t he cont roller st ops al l switching op eration s a nd e nters t he l atch m ode un til the ac plug is removed. adjustable over-temperature protection and external protection triggering C rt pin the r t pin is used to achieve over -temperature protection using an ntc resistor and provides external protection triggering for additional protection. typically, since the external protection triggerig is usua lly use d t o pr otect t he po wer syst em fr om abnormal conditions it needs a fast reaction speed or a short reaction time. therefore, the protection debounce time of the external protection triggering is set to around 100 s once the r t pin voltage is lower than 0.5v . for over temperature protection, since the temperature cannot change rapidly , the protection debounce t ime sh ould n ot b e a ctivated q uickly. t he protection debounce time for the otp is set to around 10ms. in addition, to avoid imprope r triggering due to a lightning test, the r t pin triggering voltage of the otp is set to 1.0v , which is higher than the external triggering voltage of 0.5v. det pin over-voltage protection C det ovp an output over - voltage protection is implemented by sensing the auxiliary winding voltage on the det pin. the qr ovp works by sampling the plateau voltage on the det pin after the pwm switch-off sequence. a 4s internal blanking time guarantees a clean pla - teau provided that the leakage inductance ringing has been fully damped. if the sampled plateau voltage exceeds the ovp trip level of 2.5v and lasts for t det- ovp , the de vice wi ll e nter a uto-recovery prot ection (HT7L5820) or the latch mode (ht7l5821) until the ac powe r i s re moved. t he prot ection vol tage l evel can be determined by the ratio of the external resistor divider r det1 and r det 2 , as shown in the following figure. the flat voltage on the det pin can be ex- t he f lat v oltage o n t he de t p in c an b e e x - pressed by the following equation: v det = (n a /n s )v o r det2 r det1 +r det2 plateau sampling 2.5v det auxiliary winding 10 r det1 r det2 t det-ovp recovery (HT7L5820) latched (ht7l5821) det over-voltage protection output open-loop and over-load protection to protect the circuit from being damaged during conditions of output open-loop or overload, the device includes an olp function. under such fault conditions, t he ou tput vo ltage i s de creased a nd t he sink current of the photo-coupler is reduced. this will force the fb pin voltage to increase using an internal bias. when the fb pin voltage ramps up to 4.2v for 50ms the olp protection is acti vated to turn of f the power switch and stop all switching operations. rev. 1.20 12 november 17, 2016 HT7L5820/ht7l5821 package information note that the package information provided here is for consultation purposes only . as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package information . additional supplementary information with regard to packaging is liste d below . click on the relevant section to be transferred to the relevant website page. ? further package information (include outline dimensions, product t ape and reel specifcations) ? packing meterials information ? carton information rev. 1.20 13 november 17, 2016 HT7L5820/ht7l5821 16-pin nsop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.236 bsc b 0.154 bsc c 0.012 0.020 c' 0.390 bsc d 0.069 e 0.050 bsc f 0.004 0.010 g 0.016 0.050 h 0.004 0.010 0 D 8 symbol dimensions in mm min. nom. max. a 6.000 bsc b 3.900 bsc c 0.31 0.51 c' 9.900 bsc d 1.75 e 1.270 bsc f 0.10 0.25 g 0.40 1.27 h 0.10 0.25 0 D 8 rev. 1.20 14 november 17, 2016 HT7L5820/ht7l5821 copyright ? 2016 by holtek semiconductor inc. the information appearing in this data sheet is believ ed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifcations described. the applications m entioned herein are us ed solely for the pur pose of illus tration and holtek makes no warranty or repres entation that s uch applications will be suitable without further modification, nor recommends the us e of its pr oducts for applic ation that may present a r is k to hum an life due to malfunction or otherwise. holtek's products are not authorized for use as critical c omponents in life support devices or systems. holtek reserves the right to alter its pr oducts without prior notification. for the most up-to-date information, please v is it our web site at http://www.holtek.com/en. |
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